The present invention generally relates to the field of electronic device manufacturing. More specifically, the present invention relates to techniques for enhancing thermal performance of integrated circuit (IC) packages.
As integrated circuit fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functionalities increases, however, so does the number of components on a single chip. Additional components add additional signal switching, in turn, creating more heat. Also, the complexity of these devices poses a further thermal problem where different regions on a same die may have operationally significant differences in temperature.
Thermal expansion differences have been a fundamental problem facing the semiconductor industry. The different temperature regions on the same die intensify the thermal expansion problems. During normal operation, a semiconductor device is expected to survive a fairly wide range of temperature fluctuations. While undergoing these fluctuations, if a portion of the device expands and contracts at one rate while another portion of the same device moves at vastly different rates, a great deal of stress can be generated within the combined structure. These stresses can produce failures within the components themselves or at any of the interfaces between these components.
Accordingly, performance and reliability of an IC package depends, among other things, on temperature uniformity across the circuits on a die. Temperature differences between portions of the die circuit may lead to timing problems and clock speed reductions (thereby slowing the speed of a chip). This in turn can degrade performance of the chip. In some cases, such problems may lead to soft errors where a chip may provide a wrong result without totally failing or producing any error messages.
An additional problem stems from the fact that different regions of a same die may change their thermal behavior over time. In other words, a region that may be hot at a first point in time may be considered cold at a later point, whereas an adjacent region that may have been cold at the first point in time may be hot at the later point.
A current approach in electronic cooling is to provide the best thermal path for the heat being generated within the circuitry of the IC package. As a result, areas of the die that either produce less power, or are inactive at a given time, stay significantly cooler than the areas with the maximum power generation. This causes an elevated temperature difference across the die, thereby exasperating the thermal non-uniformity issues. Removing additional heat from the xe2x80x9chotxe2x80x9d spots is impractical because the heat path used is often near its best price/performance considerations already.
The present invention includes novel methods and apparatus to enhance thermal performance of IC packages. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions.
In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.
In a yet a different embodiment, the thermal conductivity of the thermal enhancement material increases as the temperature effecting the thermal enhancement material increases.
In a further embodiment, the thermal conductivity of the thermal enhancement material decreases as the temperature effecting the thermal enhancement material decreases.
In a different embodiment, an apparatus for enhancing thermal uniformity across a semiconductor device is disclosed. The apparatus includes the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. A thermal enhancement material is located substantially adjacent to the first and second thermal regions.
In an additional embodiment, the semiconductor device is a device selected from a group comprising a die, an IC, a processor, and an ASIC.
In yet a further embodiment, the thermal enhancement material is in close proximity to at least one of the first and second thermal regions.
In yet a different embodiment, the thermal enhancement material is located within a thermal path of the semiconductor device.